Module rp2040_pac::clocks::clk_gpout3_ctrl

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Expand description

Clock control, can be changed on-the-fly (except for auxsrc)

Structs§

Enums§

  • Selects the auxiliary clock source, will glitch when switching

Type Aliases§

  • Field AUXSRC reader - Selects the auxiliary clock source, will glitch when switching
  • Field AUXSRC writer - Selects the auxiliary clock source, will glitch when switching
  • Field DC50 reader - Enables duty cycle correction for odd divisors
  • Field DC50 writer - Enables duty cycle correction for odd divisors
  • Field ENABLE reader - Starts and stops the clock generator cleanly
  • Field ENABLE writer - Starts and stops the clock generator cleanly
  • Field KILL reader - Asynchronously kills the clock generator
  • Field KILL writer - Asynchronously kills the clock generator
  • Field NUDGE reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock
    This can be done at any time
  • Field NUDGE writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock
    This can be done at any time
  • Field PHASE reader - This delays the enable signal by up to 3 cycles of the input clock
    This must be set before the clock is enabled to have any effect
  • Field PHASE writer - This delays the enable signal by up to 3 cycles of the input clock
    This must be set before the clock is enabled to have any effect
  • Register CLK_GPOUT3_CTRL reader
  • Register CLK_GPOUT3_CTRL writer