Struct rp2040_pac::SPI1

pub struct SPI1 { /* private fields */ }

SPI1

Implementations

impl SPI1

pub const PTR: *const RegisterBlock = {0x40040000 as *const spi0::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn sspcr0(&self) -> &SSPCR0

0x00 - Control register 0, SSPCR0 on page 3-4

pub fn sspcr1(&self) -> &SSPCR1

0x04 - Control register 1, SSPCR1 on page 3-5

pub fn sspdr(&self) -> &SSPDR

0x08 - Data register, SSPDR on page 3-6

pub fn sspsr(&self) -> &SSPSR

0x0c - Status register, SSPSR on page 3-7

pub fn sspcpsr(&self) -> &SSPCPSR

0x10 - Clock prescale register, SSPCPSR on page 3-8

pub fn sspimsc(&self) -> &SSPIMSC

0x14 - Interrupt mask set or clear register, SSPIMSC on page 3-9

pub fn sspris(&self) -> &SSPRIS

0x18 - Raw interrupt status register, SSPRIS on page 3-10

pub fn sspmis(&self) -> &SSPMIS

0x1c - Masked interrupt status register, SSPMIS on page 3-11

pub fn sspicr(&self) -> &SSPICR

0x20 - Interrupt clear register, SSPICR on page 3-11

pub fn sspdmacr(&self) -> &SSPDMACR

0x24 - DMA control register, SSPDMACR on page 3-12

pub fn sspperiphid0(&self) -> &SSPPERIPHID0

0xfe0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn sspperiphid1(&self) -> &SSPPERIPHID1

0xfe4 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn sspperiphid2(&self) -> &SSPPERIPHID2

0xfe8 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn sspperiphid3(&self) -> &SSPPERIPHID3

0xfec - Peripheral identification registers, SSPPeriphID0-3 on page 3-13

pub fn ssppcellid0(&self) -> &SSPPCELLID0

0xff0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

pub fn ssppcellid1(&self) -> &SSPPCELLID1

0xff4 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

pub fn ssppcellid2(&self) -> &SSPPCELLID2

0xff8 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

pub fn ssppcellid3(&self) -> &SSPPCELLID3

0xffc - PrimeCell identification registers, SSPPCellID0-3 on page 3-16

Trait Implementations

impl Debug for SPI1

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for SPI1

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for SPI1