Module pll_sys

PLL_SYS

Modules

cs

Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz

fbdiv_int

Feedback divisor
(note: this PLL does not support fractional division)

prim

Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2

pwr

Controls the PLL power modes.

Structs

RegisterBlock

Register block

Type Aliases

CS

CS (rw) register accessor: Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz

FBDIV_INT

FBDIV_INT (rw) register accessor: Feedback divisor
(note: this PLL does not support fractional division)

PRIM

PRIM (rw) register accessor: Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2

PWR

PWR (rw) register accessor: Controls the PLL power modes.