Module rp2040_pac::syscfg

Register block for various chip control signals

Modules

• dbgforce
  Directly control the SWD debug port of either processor
• mempowerdown
  Control power downs to memories. Set high to power down memories.
  Use with extreme caution
• proc0_nmi_mask
  Processor core 0 NMI source mask
  Set a bit high to enable NMI from that IRQ
• proc1_nmi_mask
  Processor core 1 NMI source mask
  Set a bit high to enable NMI from that IRQ
• proc_config
  Configuration for processors
• proc_in_sync_bypass
  For each bit, if 1, bypass the input synchronizer between that GPIO
  and the GPIO input register in the SIO. The input synchronizers should
  generally be unbypassed, to avoid injecting metastabilities into processors.
  If you’re feeling brave, you can bypass to save two cycles of input
  latency. This register applies to GPIO 0…29.
• proc_in_sync_bypass_hi
  For each bit, if 1, bypass the input synchronizer between that GPIO
  and the GPIO input register in the SIO. The input synchronizers should
  generally be unbypassed, to avoid injecting metastabilities into processors.
  If you’re feeling brave, you can bypass to save two cycles of input
  latency. This register applies to GPIO 30…35 (the QSPI IOs).

Structs

• RegisterBlock
  Register block

Type Aliases

• DBGFORCE
  DBGFORCE (rw) register accessor: Directly control the SWD debug port of either processor
• MEMPOWERDOWN
  MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories.
  Use with extreme caution
• PROC0_NMI_MASK
  PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask
  Set a bit high to enable NMI from that IRQ
• PROC1_NMI_MASK
  PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask
  Set a bit high to enable NMI from that IRQ
• PROC_CONFIG
  PROC_CONFIG (rw) register accessor: Configuration for processors
• PROC_IN_SYNC_BYPASS
  PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO
  and the GPIO input register in the SIO. The input synchronizers should
  generally be unbypassed, to avoid injecting metastabilities into processors.
  If you’re feeling brave, you can bypass to save two cycles of input
  latency. This register applies to GPIO 0…29.
• PROC_IN_SYNC_BYPASS_HI
  PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO
  and the GPIO input register in the SIO. The input synchronizers should
  generally be unbypassed, to avoid injecting metastabilities into processors.
  If you’re feeling brave, you can bypass to save two cycles of input
  latency. This register applies to GPIO 30…35 (the QSPI IOs).