Module adc

Control and data interface to SAR ADC

Modules

cs

ADC Control and Status

div

Clock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256

fcs

FIFO control and status

fifo

Conversion result FIFO

inte

Interrupt Enable

intf

Interrupt Force

intr

Raw Interrupts

ints

Interrupt status after masking & forcing

result

Result of most recent ADC conversion

Structs

RegisterBlock

Register block

Type Aliases

CS

CS (rw) register accessor: ADC Control and Status

DIV

DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256

FCS

FCS (rw) register accessor: FIFO control and status

FIFO

FIFO (r) register accessor: Conversion result FIFO

INTE

INTE (rw) register accessor: Interrupt Enable

INTF

INTF (rw) register accessor: Interrupt Force

INTR

INTR (r) register accessor: Raw Interrupts

INTS

INTS (r) register accessor: Interrupt status after masking & forcing

RESULT

RESULT (r) register accessor: Result of most recent ADC conversion