Struct rp2040_pac::CLOCKS

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pub struct CLOCKS { /* private fields */ }

Expand description

CLOCKS

Implementations§

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impl CLOCKS

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pub const PTR: const RegisterBlock = {0x40008000 as const clocks::RegisterBlock}

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn clk_gpout0_ctrl(&self) -> &CLK_GPOUT0_CTRL

0x00 - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_gpout0_div(&self) -> &CLK_GPOUT0_DIV

0x04 - Clock divisor, can be changed on-the-fly

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pub fn clk_gpout0_selected(&self) -> &CLK_GPOUT0_SELECTED

0x08 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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pub fn clk_gpout1_ctrl(&self) -> &CLK_GPOUT1_CTRL

0x0c - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_gpout1_div(&self) -> &CLK_GPOUT1_DIV

0x10 - Clock divisor, can be changed on-the-fly

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pub fn clk_gpout1_selected(&self) -> &CLK_GPOUT1_SELECTED

0x14 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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pub fn clk_gpout2_ctrl(&self) -> &CLK_GPOUT2_CTRL

0x18 - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_gpout2_div(&self) -> &CLK_GPOUT2_DIV

0x1c - Clock divisor, can be changed on-the-fly

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pub fn clk_gpout2_selected(&self) -> &CLK_GPOUT2_SELECTED

0x20 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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pub fn clk_gpout3_ctrl(&self) -> &CLK_GPOUT3_CTRL

0x24 - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_gpout3_div(&self) -> &CLK_GPOUT3_DIV

0x28 - Clock divisor, can be changed on-the-fly

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pub fn clk_gpout3_selected(&self) -> &CLK_GPOUT3_SELECTED

0x2c - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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pub fn clk_ref_ctrl(&self) -> &CLK_REF_CTRL

0x30 - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_ref_div(&self) -> &CLK_REF_DIV

0x34 - Clock divisor, can be changed on-the-fly

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pub fn clk_ref_selected(&self) -> &CLK_REF_SELECTED

0x38 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

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pub fn clk_sys_ctrl(&self) -> &CLK_SYS_CTRL

0x3c - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_sys_div(&self) -> &CLK_SYS_DIV

0x40 - Clock divisor, can be changed on-the-fly

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pub fn clk_sys_selected(&self) -> &CLK_SYS_SELECTED

0x44 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

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pub fn clk_peri_ctrl(&self) -> &CLK_PERI_CTRL

0x48 - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_peri_selected(&self) -> &CLK_PERI_SELECTED

0x50 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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pub fn clk_usb_ctrl(&self) -> &CLK_USB_CTRL

0x54 - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_usb_div(&self) -> &CLK_USB_DIV

0x58 - Clock divisor, can be changed on-the-fly

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pub fn clk_usb_selected(&self) -> &CLK_USB_SELECTED

0x5c - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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pub fn clk_adc_ctrl(&self) -> &CLK_ADC_CTRL

0x60 - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_adc_div(&self) -> &CLK_ADC_DIV

0x64 - Clock divisor, can be changed on-the-fly

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pub fn clk_adc_selected(&self) -> &CLK_ADC_SELECTED

0x68 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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pub fn clk_rtc_ctrl(&self) -> &CLK_RTC_CTRL

0x6c - Clock control, can be changed on-the-fly (except for auxsrc)

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pub fn clk_rtc_div(&self) -> &CLK_RTC_DIV

0x70 - Clock divisor, can be changed on-the-fly

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pub fn clk_rtc_selected(&self) -> &CLK_RTC_SELECTED

0x74 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

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