This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
You can read
this register and get clk_gpout1_selected::R
. See API.
For information about available fields see clk_gpout1_selected
module
struct CLK_GPOUT1_SELECTED { /* private fields */ }