Module rp2040_pac::i2c0

DW_apb_i2c address block

List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are fixed values, set at hardware design time):

IC_ULTRA_FAST_MODE ……………. 0x0
IC_UFM_TBUF_CNT_DEFAULT ……….. 0x8
IC_UFM_SCL_LOW_COUNT ………….. 0x0008
IC_UFM_SCL_HIGH_COUNT …………. 0x0006
IC_TX_TL …………………….. 0x0
IC_TX_CMD_BLOCK ………………. 0x1
IC_HAS_DMA …………………… 0x1
IC_HAS_ASYNC_FIFO …………….. 0x0
IC_SMBUS_ARP …………………. 0x0
IC_FIRST_DATA_BYTE_STATUS ……… 0x1
IC_INTR_IO …………………… 0x1
IC_MASTER_MODE ……………….. 0x1
IC_DEFAULT_ACK_GENERAL_CALL ……. 0x1
IC_INTR_POL ………………….. 0x1
IC_OPTIONAL_SAR ………………. 0x0
IC_DEFAULT_TAR_SLAVE_ADDR ……… 0x055
IC_DEFAULT_SLAVE_ADDR …………. 0x055
IC_DEFAULT_HS_SPKLEN ………….. 0x1
IC_FS_SCL_HIGH_COUNT ………….. 0x0006
IC_HS_SCL_LOW_COUNT …………… 0x0008
IC_DEVICE_ID_VALUE ……………. 0x0
IC_10BITADDR_MASTER …………… 0x0
IC_CLK_FREQ_OPTIMIZATION ………. 0x0
IC_DEFAULT_FS_SPKLEN ………….. 0x7
IC_ADD_ENCODED_PARAMS …………. 0x0
IC_DEFAULT_SDA_HOLD …………… 0x000001
IC_DEFAULT_SDA_SETUP ………….. 0x64
IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
IC_CLOCK_PERIOD ………………. 100
IC_EMPTYFIFO_HOLD_MASTER_EN ……. 1
IC_RESTART_EN ………………… 0x1
IC_TX_CMD_BLOCK_DEFAULT ……….. 0x0
IC_BUS_CLEAR_FEATURE ………….. 0x0
IC_CAP_LOADING ……………….. 100
IC_FS_SCL_LOW_COUNT …………… 0x000d
APB_DATA_WIDTH ……………….. 32
IC_SDA_STUCK_TIMEOUT_DEFAULT …… 0xffffffff
IC_SLV_DATA_NACK_ONLY …………. 0x1
IC_10BITADDR_SLAVE ……………. 0x0
IC_CLK_TYPE ………………….. 0x0
IC_SMBUS_UDID_MSB …………….. 0x0
IC_SMBUS_SUSPEND_ALERT ………… 0x0
IC_HS_SCL_HIGH_COUNT ………….. 0x0006
IC_SLV_RESTART_DET_EN …………. 0x1
IC_SMBUS …………………….. 0x0
IC_OPTIONAL_SAR_DEFAULT ……….. 0x0
IC_PERSISTANT_SLV_ADDR_DEFAULT …. 0x0
IC_USE_COUNTS ………………… 0x0
IC_RX_BUFFER_DEPTH ……………. 16
IC_SCL_STUCK_TIMEOUT_DEFAULT …… 0xffffffff
IC_RX_FULL_HLD_BUS_EN …………. 0x1
IC_SLAVE_DISABLE ……………… 0x1
IC_RX_TL …………………….. 0x0
IC_DEVICE_ID …………………. 0x0
IC_HC_COUNT_VALUES ……………. 0x0
I2C_DYNAMIC_TAR_UPDATE ………… 0
IC_SMBUS_CLK_LOW_MEXT_DEFAULT ….. 0xffffffff
IC_SMBUS_CLK_LOW_SEXT_DEFAULT ….. 0xffffffff
IC_HS_MASTER_CODE …………….. 0x1
IC_SMBUS_RST_IDLE_CNT_DEFAULT ….. 0xffff
IC_SMBUS_UDID_LSB_DEFAULT ……… 0xffffffff
IC_SS_SCL_HIGH_COUNT ………….. 0x0028
IC_SS_SCL_LOW_COUNT …………… 0x002f
IC_MAX_SPEED_MODE …………….. 0x2
IC_STAT_FOR_CLK_STRETCH ……….. 0x0
IC_STOP_DET_IF_MASTER_ACTIVE …… 0x0
IC_DEFAULT_UFM_SPKLEN …………. 0x1
IC_TX_BUFFER_DEPTH ……………. 16

Modules

• ic_ack_general_call
  I2C ACK General Call Register
• ic_clr_activity
  Clear ACTIVITY Interrupt Register
• ic_clr_gen_call
  Clear GEN_CALL Interrupt Register
• ic_clr_intr
  Clear Combined and Individual Interrupt Register
• ic_clr_rd_req
  Clear RD_REQ Interrupt Register
• ic_clr_restart_det
  Clear RESTART_DET Interrupt Register
• ic_clr_rx_done
  Clear RX_DONE Interrupt Register
• ic_clr_rx_over
  Clear RX_OVER Interrupt Register
• ic_clr_rx_under
  Clear RX_UNDER Interrupt Register
• ic_clr_start_det
  Clear START_DET Interrupt Register
• ic_clr_stop_det
  Clear STOP_DET Interrupt Register
• ic_clr_tx_abrt
  Clear TX_ABRT Interrupt Register
• ic_clr_tx_over
  Clear TX_OVER Interrupt Register
• ic_comp_param_1
  Component Parameter Register 1
• ic_comp_type
  I2C Component Type Register
• ic_comp_version
  I2C Component Version Register
• ic_con
  I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
• ic_data_cmd
  I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
• ic_dma_cr
  DMA Control Register
• ic_dma_rdlr
  I2C Receive Data Level Register
• ic_dma_tdlr
  DMA Transmit Data Level Register
• ic_enable
  I2C Enable Register
• ic_enable_status
  I2C Enable Status Register
• ic_fs_scl_hcnt
  Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
• ic_fs_scl_lcnt
  Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
• ic_fs_spklen
  I2C SS, FS or FM+ spike suppression limit
• ic_intr_mask
  I2C Interrupt Mask Register.
• ic_intr_stat
  I2C Interrupt Status Register
• ic_raw_intr_stat
  I2C Raw Interrupt Status Register
• ic_rx_tl
  I2C Receive FIFO Threshold Register
• ic_rxflr
  I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
• ic_sar
  I2C Slave Address Register
• ic_sda_hold
  I2C SDA Hold Time Length Register
• ic_sda_setup
  I2C SDA Setup Register
• ic_slv_data_nack_only
  Generate Slave Data NACK Register
• ic_ss_scl_hcnt
  Standard Speed I2C Clock SCL High Count Register
• ic_ss_scl_lcnt
  Standard Speed I2C Clock SCL Low Count Register
• ic_status
  I2C Status Register
• ic_tar
  I2C Target Address Register
• ic_tx_abrt_source
  I2C Transmit Abort Source Register
• ic_tx_tl
  I2C Transmit FIFO Threshold Register
• ic_txflr
  I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.

Structs

• RegisterBlock
  Register block

Type Aliases

• IC_ACK_GENERAL_CALL
  IC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK General Call Register
• IC_CLR_ACTIVITY
  IC_CLR_ACTIVITY (r) register accessor: Clear ACTIVITY Interrupt Register
• IC_CLR_GEN_CALL
  IC_CLR_GEN_CALL (r) register accessor: Clear GEN_CALL Interrupt Register
• IC_CLR_INTR
  IC_CLR_INTR (r) register accessor: Clear Combined and Individual Interrupt Register
• IC_CLR_RD_REQ
  IC_CLR_RD_REQ (r) register accessor: Clear RD_REQ Interrupt Register
• IC_CLR_RESTART_DET
  IC_CLR_RESTART_DET (r) register accessor: Clear RESTART_DET Interrupt Register
• IC_CLR_RX_DONE
  IC_CLR_RX_DONE (r) register accessor: Clear RX_DONE Interrupt Register
• IC_CLR_RX_OVER
  IC_CLR_RX_OVER (r) register accessor: Clear RX_OVER Interrupt Register
• IC_CLR_RX_UNDER
  IC_CLR_RX_UNDER (r) register accessor: Clear RX_UNDER Interrupt Register
• IC_CLR_START_DET
  IC_CLR_START_DET (r) register accessor: Clear START_DET Interrupt Register
• IC_CLR_STOP_DET
  IC_CLR_STOP_DET (r) register accessor: Clear STOP_DET Interrupt Register
• IC_CLR_TX_ABRT
  IC_CLR_TX_ABRT (r) register accessor: Clear TX_ABRT Interrupt Register
• IC_CLR_TX_OVER
  IC_CLR_TX_OVER (r) register accessor: Clear TX_OVER Interrupt Register
• IC_COMP_PARAM_1
  IC_COMP_PARAM_1 (r) register accessor: Component Parameter Register 1
• IC_COMP_TYPE
  IC_COMP_TYPE (r) register accessor: I2C Component Type Register
• IC_COMP_VERSION
  IC_COMP_VERSION (r) register accessor: I2C Component Version Register
• IC_CON
  IC_CON (rw) register accessor: I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
• IC_DATA_CMD
  IC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
• IC_DMA_CR
  IC_DMA_CR (rw) register accessor: DMA Control Register
• IC_DMA_RDLR
  IC_DMA_RDLR (rw) register accessor: I2C Receive Data Level Register
• IC_DMA_TDLR
  IC_DMA_TDLR (rw) register accessor: DMA Transmit Data Level Register
• IC_ENABLE
  IC_ENABLE (rw) register accessor: I2C Enable Register
• IC_ENABLE_STATUS
  IC_ENABLE_STATUS (r) register accessor: I2C Enable Status Register
• IC_FS_SCL_HCNT
  IC_FS_SCL_HCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
• IC_FS_SCL_LCNT
  IC_FS_SCL_LCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
• IC_FS_SPKLEN
  IC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ spike suppression limit
• IC_INTR_MASK
  IC_INTR_MASK (rw) register accessor: I2C Interrupt Mask Register.
• IC_INTR_STAT
  IC_INTR_STAT (r) register accessor: I2C Interrupt Status Register
• IC_RAW_INTR_STAT
  IC_RAW_INTR_STAT (r) register accessor: I2C Raw Interrupt Status Register
• IC_RXFLR
  IC_RXFLR (r) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
• IC_RX_TL
  IC_RX_TL (rw) register accessor: I2C Receive FIFO Threshold Register
• IC_SAR
  IC_SAR (rw) register accessor: I2C Slave Address Register
• IC_SDA_HOLD
  IC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time Length Register
• IC_SDA_SETUP
  IC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register
• IC_SLV_DATA_NACK_ONLY
  IC_SLV_DATA_NACK_ONLY (rw) register accessor: Generate Slave Data NACK Register
• IC_SS_SCL_HCNT
  IC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C Clock SCL High Count Register
• IC_SS_SCL_LCNT
  IC_SS_SCL_LCNT (rw) register accessor: Standard Speed I2C Clock SCL Low Count Register
• IC_STATUS
  IC_STATUS (r) register accessor: I2C Status Register
• IC_TAR
  IC_TAR (rw) register accessor: I2C Target Address Register
• IC_TXFLR
  IC_TXFLR (r) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
• IC_TX_ABRT_SOURCE
  IC_TX_ABRT_SOURCE (r) register accessor: I2C Transmit Abort Source Register
• IC_TX_TL
  IC_TX_TL (rw) register accessor: I2C Transmit FIFO Threshold Register