Type Alias rp2040_pac::clocks::CLK_SYS_DIV

pub type CLK_SYS_DIV = Reg<CLK_SYS_DIV_SPEC>;

CLK_SYS_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly

You can read this register and get clk_sys_div::R. You can reset, write, write_with_zero this register using clk_sys_div::W. You can also modify this register. See API.

For information about available fields see clk_sys_div module

Aliased Type

struct CLK_SYS_DIV { /* private fields */ }