Module rp2040_pac::spi0
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SPI0
Modules§
- Clock prescale register, SSPCPSR on page 3-8
- Control register 0, SSPCR0 on page 3-4
- Control register 1, SSPCR1 on page 3-5
- DMA control register, SSPDMACR on page 3-12
- Data register, SSPDR on page 3-6
- Interrupt clear register, SSPICR on page 3-11
- Interrupt mask set or clear register, SSPIMSC on page 3-9
- Masked interrupt status register, SSPMIS on page 3-11
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Raw interrupt status register, SSPRIS on page 3-10
- Status register, SSPSR on page 3-7
Structs§
- Register block
Type Aliases§
- SSPCPSR (rw) register accessor: Clock prescale register, SSPCPSR on page 3-8
- SSPCR0 (rw) register accessor: Control register 0, SSPCR0 on page 3-4
- SSPCR1 (rw) register accessor: Control register 1, SSPCR1 on page 3-5
- SSPDMACR (rw) register accessor: DMA control register, SSPDMACR on page 3-12
- SSPDR (rw) register accessor: Data register, SSPDR on page 3-6
- SSPICR (rw) register accessor: Interrupt clear register, SSPICR on page 3-11
- SSPIMSC (rw) register accessor: Interrupt mask set or clear register, SSPIMSC on page 3-9
- SSPMIS (r) register accessor: Masked interrupt status register, SSPMIS on page 3-11
- SSPPCELLID0 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPCELLID1 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPCELLID2 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPCELLID3 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPERIPHID0 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPPERIPHID1 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPPERIPHID2 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPPERIPHID3 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPRIS (r) register accessor: Raw interrupt status register, SSPRIS on page 3-10
- SSPSR (r) register accessor: Status register, SSPSR on page 3-7