Expand description
SPI0
Modules§
- sspcpsr
- Clock prescale register, SSPCPSR on page 3-8
- sspcr0
- Control register 0, SSPCR0 on page 3-4
- sspcr1
- Control register 1, SSPCR1 on page 3-5
- sspdmacr
- DMA control register, SSPDMACR on page 3-12
- sspdr
- Data register, SSPDR on page 3-6
- sspicr
- Interrupt clear register, SSPICR on page 3-11
- sspimsc
- Interrupt mask set or clear register, SSPIMSC on page 3-9
- sspmis
- Masked interrupt status register, SSPMIS on page 3-11
- ssppcellid0
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- ssppcellid1
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- ssppcellid2
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- ssppcellid3
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- sspperiphid0
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- sspperiphid1
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- sspperiphid2
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- sspperiphid3
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- sspris
- Raw interrupt status register, SSPRIS on page 3-10
- sspsr
- Status register, SSPSR on page 3-7
Structs§
- Register
Block - Register block
Type Aliases§
- SSPCPSR
- SSPCPSR (rw) register accessor: Clock prescale register, SSPCPSR on page 3-8
- SSPCR0
- SSPCR0 (rw) register accessor: Control register 0, SSPCR0 on page 3-4
- SSPCR1
- SSPCR1 (rw) register accessor: Control register 1, SSPCR1 on page 3-5
- SSPDMACR
- SSPDMACR (rw) register accessor: DMA control register, SSPDMACR on page 3-12
- SSPDR
- SSPDR (rw) register accessor: Data register, SSPDR on page 3-6
- SSPICR
- SSPICR (rw) register accessor: Interrupt clear register, SSPICR on page 3-11
- SSPIMSC
- SSPIMSC (rw) register accessor: Interrupt mask set or clear register, SSPIMSC on page 3-9
- SSPMIS
- SSPMIS (r) register accessor: Masked interrupt status register, SSPMIS on page 3-11
- SSPPCELLI
D0 - SSPPCELLID0 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPCELLI
D1 - SSPPCELLID1 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPCELLI
D2 - SSPPCELLID2 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPCELLI
D3 - SSPPCELLID3 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- SSPPERIPHI
D0 - SSPPERIPHID0 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPPERIPHI
D1 - SSPPERIPHID1 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPPERIPHI
D2 - SSPPERIPHID2 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPPERIPHI
D3 - SSPPERIPHID3 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- SSPRIS
- SSPRIS (r) register accessor: Raw interrupt status register, SSPRIS on page 3-10
- SSPSR
- SSPSR (r) register accessor: Status register, SSPSR on page 3-7