Module clk_gpout0_ctrl

Clock control, can be changed on-the-fly (except for auxsrc)

Structs

CLK_GPOUT0_CTRL_SPEC

Clock control, can be changed on-the-fly (except for auxsrc)

Enums

AUXSRC_A

Selects the auxiliary clock source, will glitch when switching

Type Aliases

AUXSRC_R

Field AUXSRC reader - Selects the auxiliary clock source, will glitch when switching

AUXSRC_W

Field AUXSRC writer - Selects the auxiliary clock source, will glitch when switching

DC50_R

Field DC50 reader - Enables duty cycle correction for odd divisors

DC50_W

Field DC50 writer - Enables duty cycle correction for odd divisors

ENABLE_R

Field ENABLE reader - Starts and stops the clock generator cleanly

ENABLE_W

Field ENABLE writer - Starts and stops the clock generator cleanly

KILL_R

Field KILL reader - Asynchronously kills the clock generator

KILL_W

Field KILL writer - Asynchronously kills the clock generator

NUDGE_R

Field NUDGE reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time

NUDGE_W

Field NUDGE writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time

PHASE_R

Field PHASE reader - This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect

PHASE_W

Field PHASE writer - This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect

R

Register CLK_GPOUT0_CTRL reader

W

Register CLK_GPOUT0_CTRL writer