Module ppb

PPB

Modules

aircr

Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.

ccr

The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.

cpuid

Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.

icsr

Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.

mpu_ctrl

Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.

mpu_rasr

Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.

mpu_rbar

Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.

mpu_rnr

Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.

mpu_type

Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.

nvic_icer

Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.

nvic_icpr

Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.

nvic_ipr0

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
These registers are only word-accessible

nvic_ipr1

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr2

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr3

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr4

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr5

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr6

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_ipr7

Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

nvic_iser

Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.

nvic_ispr

The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.

scr

System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.

shcsr

Use the System Handler Control and State Register to determine or clear the pending status of SVCall.

shpr2

System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.

shpr3

System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.

syst_calib

Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.

syst_csr

Use the SysTick Control and Status Register to enable the SysTick features.

syst_cvr

Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.

syst_rvr

Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.

vtor

The VTOR holds the vector table offset address.

Structs

RegisterBlock

Register block

Type Aliases

AIRCR

AIRCR (rw) register accessor: Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.

CCR

CCR (r) register accessor: The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.

CPUID

CPUID (r) register accessor: Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.

ICSR

ICSR (rw) register accessor: Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.

MPU_CTRL

MPU_CTRL (rw) register accessor: Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.

MPU_RASR

MPU_RASR (rw) register accessor: Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.

MPU_RBAR

MPU_RBAR (rw) register accessor: Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.

MPU_RNR

MPU_RNR (rw) register accessor: Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.

MPU_TYPE

MPU_TYPE (r) register accessor: Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.

NVIC_ICER

NVIC_ICER (rw) register accessor: Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.

NVIC_ICPR

NVIC_ICPR (rw) register accessor: Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.

NVIC_IPR0

NVIC_IPR0 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
These registers are only word-accessible

NVIC_IPR1

NVIC_IPR1 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

NVIC_IPR2

NVIC_IPR2 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

NVIC_IPR3

NVIC_IPR3 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

NVIC_IPR4

NVIC_IPR4 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

NVIC_IPR5

NVIC_IPR5 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

NVIC_IPR6

NVIC_IPR6 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

NVIC_IPR7

NVIC_IPR7 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.

NVIC_ISER

NVIC_ISER (rw) register accessor: Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.

NVIC_ISPR

NVIC_ISPR (rw) register accessor: The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.

SCR

SCR (rw) register accessor: System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.

SHCSR

SHCSR (rw) register accessor: Use the System Handler Control and State Register to determine or clear the pending status of SVCall.

SHPR2

SHPR2 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.

SHPR3

SHPR3 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.

SYST_CALIB

SYST_CALIB (r) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.

SYST_CSR

SYST_CSR (rw) register accessor: Use the SysTick Control and Status Register to enable the SysTick features.

SYST_CVR

SYST_CVR (rw) register accessor: Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.

SYST_RVR

SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.

VTOR

VTOR (rw) register accessor: The VTOR holds the vector table offset address.