Type Alias rp2040_pac::sio::FIFO_ST

pub type FIFO_ST = Reg<FIFO_ST_SPEC>;

FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

You can read this register and get fifo_st::R. You can reset, write, write_with_zero this register using fifo_st::W. You can also modify this register. See API.

For information about available fields see fifo_st module

Aliased Type

struct FIFO_ST { /* private fields */ }