Type Alias rp2040_pac::sio::INTERP0_BASE_1AND0

pub type INTERP0_BASE_1AND0 = Reg<INTERP0_BASE_1AND0_SPEC>;

INTERP0_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

You can reset, write, write_with_zero this register using interp0_base_1and0::W. See API.

For information about available fields see interp0_base_1and0 module

Aliased Type

struct INTERP0_BASE_1AND0 { /* private fields */ }