Struct rp2040_pac::sio::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn cpuid(&self) -> &CPUID

0x00 - Processor core identifier
Value is 0 when read from processor core 0, and 1 when read from processor core 1.

pub const fn gpio_in(&self) -> &GPIO_IN

0x04 - Input value for GPIO pins

pub const fn gpio_hi_in(&self) -> &GPIO_HI_IN

0x08 - Input value for QSPI pins

pub const fn gpio_out(&self) -> &GPIO_OUT

0x10 - GPIO output value

pub const fn gpio_out_set(&self) -> &GPIO_OUT_SET

0x14 - GPIO output value set

pub const fn gpio_out_clr(&self) -> &GPIO_OUT_CLR

0x18 - GPIO output value clear

pub const fn gpio_out_xor(&self) -> &GPIO_OUT_XOR

0x1c - GPIO output value XOR

pub const fn gpio_oe(&self) -> &GPIO_OE

0x20 - GPIO output enable

pub const fn gpio_oe_set(&self) -> &GPIO_OE_SET

0x24 - GPIO output enable set

pub const fn gpio_oe_clr(&self) -> &GPIO_OE_CLR

0x28 - GPIO output enable clear

pub const fn gpio_oe_xor(&self) -> &GPIO_OE_XOR

0x2c - GPIO output enable XOR

pub const fn gpio_hi_out(&self) -> &GPIO_HI_OUT

0x30 - QSPI output value

pub const fn gpio_hi_out_set(&self) -> &GPIO_HI_OUT_SET

0x34 - QSPI output value set

pub const fn gpio_hi_out_clr(&self) -> &GPIO_HI_OUT_CLR

0x38 - QSPI output value clear

pub const fn gpio_hi_out_xor(&self) -> &GPIO_HI_OUT_XOR

0x3c - QSPI output value XOR

pub const fn gpio_hi_oe(&self) -> &GPIO_HI_OE

0x40 - QSPI output enable

pub const fn gpio_hi_oe_set(&self) -> &GPIO_HI_OE_SET

0x44 - QSPI output enable set

pub const fn gpio_hi_oe_clr(&self) -> &GPIO_HI_OE_CLR

0x48 - QSPI output enable clear

pub const fn gpio_hi_oe_xor(&self) -> &GPIO_HI_OE_XOR

0x4c - QSPI output enable XOR

pub const fn fifo_st(&self) -> &FIFO_ST

0x50 - Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

pub const fn fifo_wr(&self) -> &FIFO_WR

0x54 - Write access to this core’s TX FIFO

pub const fn fifo_rd(&self) -> &FIFO_RD

0x58 - Read access to this core’s RX FIFO

pub const fn spinlock_st(&self) -> &SPINLOCK_ST

0x5c - Spinlock state
A bitmap containing the state of all 32 spinlocks (1=locked).
Mainly intended for debugging.

pub const fn div_udividend(&self) -> &DIV_UDIVIDEND

0x60 - Divider unsigned dividend
Write to the DIVIDEND operand of the divider, i.e. the p in p / q.
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
unsigned calculation, and the S alias starts a signed calculation.

pub const fn div_udivisor(&self) -> &DIV_UDIVISOR

0x64 - Divider unsigned divisor
Write to the DIVISOR operand of the divider, i.e. the q in p / q.
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
unsigned calculation, and the S alias starts a signed calculation.

pub const fn div_sdividend(&self) -> &DIV_SDIVIDEND

0x68 - Divider signed dividend
The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.

pub const fn div_sdivisor(&self) -> &DIV_SDIVISOR

0x6c - Divider signed divisor
The same as UDIVISOR, but starts a signed calculation, rather than unsigned.

pub const fn div_quotient(&self) -> &DIV_QUOTIENT

0x70 - Divider result quotient
The result of DIVIDEND / DIVISOR (division). Contents undefined while CSR_READY is low.
For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
This register can be written to directly, for context save/restore purposes. This halts any
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
REMAINDER, QUOTIENT if CSR_DIRTY is used.

pub const fn div_remainder(&self) -> &DIV_REMAINDER

0x74 - Divider result remainder
The result of DIVIDEND % DIVISOR (modulo). Contents undefined while CSR_READY is low.
For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
This register can be written to directly, for context save/restore purposes. This halts any
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.

pub const fn div_csr(&self) -> &DIV_CSR

0x78 - Control and status register for divider.

pub const fn interp0_accum0(&self) -> &INTERP0_ACCUM0

0x80 - Read/write access to accumulator 0

pub const fn interp0_accum1(&self) -> &INTERP0_ACCUM1

0x84 - Read/write access to accumulator 1

pub const fn interp0_base0(&self) -> &INTERP0_BASE0

0x88 - Read/write access to BASE0 register.

pub const fn interp0_base1(&self) -> &INTERP0_BASE1

0x8c - Read/write access to BASE1 register.

pub const fn interp0_base2(&self) -> &INTERP0_BASE2

0x90 - Read/write access to BASE2 register.

pub const fn interp0_pop_lane0(&self) -> &INTERP0_POP_LANE0

0x94 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp0_pop_lane1(&self) -> &INTERP0_POP_LANE1

0x98 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp0_pop_full(&self) -> &INTERP0_POP_FULL

0x9c - Read FULL result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp0_peek_lane0(&self) -> &INTERP0_PEEK_LANE0

0xa0 - Read LANE0 result, without altering any internal state (PEEK).

pub const fn interp0_peek_lane1(&self) -> &INTERP0_PEEK_LANE1

0xa4 - Read LANE1 result, without altering any internal state (PEEK).

pub const fn interp0_peek_full(&self) -> &INTERP0_PEEK_FULL

0xa8 - Read FULL result, without altering any internal state (PEEK).

pub const fn interp0_ctrl_lane0(&self) -> &INTERP0_CTRL_LANE0

0xac - Control register for lane 0

pub const fn interp0_ctrl_lane1(&self) -> &INTERP0_CTRL_LANE1

0xb0 - Control register for lane 1

pub const fn interp0_accum0_add(&self) -> &INTERP0_ACCUM0_ADD

0xb4 - Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).

pub const fn interp0_accum1_add(&self) -> &INTERP0_ACCUM1_ADD

0xb8 - Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).

pub const fn interp0_base_1and0(&self) -> &INTERP0_BASE_1AND0

0xbc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

pub const fn interp1_accum0(&self) -> &INTERP1_ACCUM0

0xc0 - Read/write access to accumulator 0

pub const fn interp1_accum1(&self) -> &INTERP1_ACCUM1

0xc4 - Read/write access to accumulator 1

pub const fn interp1_base0(&self) -> &INTERP1_BASE0

0xc8 - Read/write access to BASE0 register.

pub const fn interp1_base1(&self) -> &INTERP1_BASE1

0xcc - Read/write access to BASE1 register.

pub const fn interp1_base2(&self) -> &INTERP1_BASE2

0xd0 - Read/write access to BASE2 register.

pub const fn interp1_pop_lane0(&self) -> &INTERP1_POP_LANE0

0xd4 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp1_pop_lane1(&self) -> &INTERP1_POP_LANE1

0xd8 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp1_pop_full(&self) -> &INTERP1_POP_FULL

0xdc - Read FULL result, and simultaneously write lane results to both accumulators (POP).

pub const fn interp1_peek_lane0(&self) -> &INTERP1_PEEK_LANE0

0xe0 - Read LANE0 result, without altering any internal state (PEEK).

pub const fn interp1_peek_lane1(&self) -> &INTERP1_PEEK_LANE1

0xe4 - Read LANE1 result, without altering any internal state (PEEK).

pub const fn interp1_peek_full(&self) -> &INTERP1_PEEK_FULL

0xe8 - Read FULL result, without altering any internal state (PEEK).

pub const fn interp1_ctrl_lane0(&self) -> &INTERP1_CTRL_LANE0

0xec - Control register for lane 0

pub const fn interp1_ctrl_lane1(&self) -> &INTERP1_CTRL_LANE1

0xf0 - Control register for lane 1

pub const fn interp1_accum0_add(&self) -> &INTERP1_ACCUM0_ADD

0xf4 - Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).

pub const fn interp1_accum1_add(&self) -> &INTERP1_ACCUM1_ADD

0xf8 - Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).

pub const fn interp1_base_1and0(&self) -> &INTERP1_BASE_1AND0

0xfc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

pub const fn spinlock(&self, n: usize) -> &SPINLOCK

0x100..0x180 - Reading from a spinlock address will:

• Return 0 if lock is already locked
• Otherwise return nonzero, and simultaneously claim the lock

Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
The value returned on success is 0x1 << lock number.

pub fn spinlock_iter(&self) -> impl Iterator<Item = &SPINLOCK>

Iterator for array of: 0x100..0x180 - Reading from a spinlock address will:

• Return 0 if lock is already locked
• Otherwise return nonzero, and simultaneously claim the lock

Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
The value returned on success is 0x1 << lock number.