Module rp2040_pac::sio::interp0_ctrl_lane1

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Expand description

Control register for lane 1

Structs§

Type Aliases§

  • Field ADD_RAW reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
  • Field ADD_RAW writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
  • Field CROSS_INPUT reader - If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.
    Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
  • Field CROSS_INPUT writer - If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.
    Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
  • Field CROSS_RESULT reader - If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
  • Field CROSS_RESULT writer - If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
  • Field FORCE_MSB reader - ORed into bits 29:28 of the lane result presented to the processor on the bus.
    No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
    of pointers into flash or SRAM.
  • Field FORCE_MSB writer - ORed into bits 29:28 of the lane result presented to the processor on the bus.
    No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
    of pointers into flash or SRAM.
  • Field MASK_LSB reader - The least-significant bit allowed to pass by the mask (inclusive)
  • Field MASK_LSB writer - The least-significant bit allowed to pass by the mask (inclusive)
  • Field MASK_MSB reader - The most-significant bit allowed to pass by the mask (inclusive)
    Setting MSB < LSB may cause chip to turn inside-out
  • Field MASK_MSB writer - The most-significant bit allowed to pass by the mask (inclusive)
    Setting MSB < LSB may cause chip to turn inside-out
  • Register INTERP0_CTRL_LANE1 reader
  • Field SHIFT reader - Logical right-shift applied to accumulator before masking
  • Field SHIFT writer - Logical right-shift applied to accumulator before masking
  • Field SIGNED reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
    before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
  • Field SIGNED writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
    before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
  • Register INTERP0_CTRL_LANE1 writer