Struct rp2040_pac::pll_sys::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn cs(&self) -> &CS

0x00 - Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz

pub const fn pwr(&self) -> &PWR

0x04 - Controls the PLL power modes.

pub const fn fbdiv_int(&self) -> &FBDIV_INT

0x08 - Feedback divisor
(note: this PLL does not support fractional division)

pub const fn prim(&self) -> &PRIM

0x0c - Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2