Type Alias rp2040_pac::pll_sys::CS

pub type CS = Reg<CS_SPEC>;

CS (rw) register accessor: Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz

You can read this register and get cs::R. You can reset, write, write_with_zero this register using cs::W. You can also modify this register. See API.

For information about available fields see cs module

Aliased Type

struct CS { /* private fields */ }