Module rp2040_pac::pll_sys::cs

Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz

Structs

• CS_SPEC
  Control and Status
  GENERAL CONSTRAINTS:
  Reference clock frequency min=5MHz, max=800MHz
  Feedback divider min=16, max=320
  VCO frequency min=750MHz, max=1600MHz

Type Aliases

• BYPASS_R
  Field BYPASS reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
• BYPASS_W
  Field BYPASS writer - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
• LOCK_R
  Field LOCK reader - PLL is locked
• R
  Register CS reader
• REFDIV_R
  Field REFDIV reader - Divides the PLL input reference clock.
  Behaviour is undefined for div=0.
  PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
• REFDIV_W
  Field REFDIV writer - Divides the PLL input reference clock.
  Behaviour is undefined for div=0.
  PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
• W
  Register CS writer