Module rp2040_pac::syscfg::proc_in_sync_bypass

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Expand description

For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0…29.

Structs§

  • For each bit, if 1, bypass the input synchronizer between that GPIO
    and the GPIO input register in the SIO. The input synchronizers should
    generally be unbypassed, to avoid injecting metastabilities into processors.
    If you’re feeling brave, you can bypass to save two cycles of input
    latency. This register applies to GPIO 0…29.

Type Aliases§