Module proc_in_sync_bypass_hi

For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30…35 (the QSPI IOs).

Structs

PROC_IN_SYNC_BYPASS_HI_SPEC

For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30…35 (the QSPI IOs).

Type Aliases

PROC_IN_SYNC_BYPASS_HI_R

Field PROC_IN_SYNC_BYPASS_HI reader -

PROC_IN_SYNC_BYPASS_HI_W

Field PROC_IN_SYNC_BYPASS_HI writer -

R

Register PROC_IN_SYNC_BYPASS_HI reader

W

Register PROC_IN_SYNC_BYPASS_HI writer