Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
These registers are only word-accessible
IP_0
reader - Priority of interrupt 0IP_0
writer - Priority of interrupt 0IP_1
reader - Priority of interrupt 1IP_1
writer - Priority of interrupt 1IP_2
reader - Priority of interrupt 2IP_2
writer - Priority of interrupt 2IP_3
reader - Priority of interrupt 3IP_3
writer - Priority of interrupt 3NVIC_IPR0
readerNVIC_IPR0
writer