Type Alias rp2040_pac::adc::DIV

pub type DIV = Reg<DIV_SPEC>;

DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256

You can read this register and get div::R. You can reset, write, write_with_zero this register using div::W. You can also modify this register. See API.

For information about available fields see div module

Aliased Type

struct DIV { /* private fields */ }