Module rp2040_pac::i2c0::ic_data_cmd

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Expand description

I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.

The size of the register changes as follows:

Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.

Structs§

  • IC_DATA_CMD_SPEC
    I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.

Enums§

  • CMD_A
    This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
  • FIRST_DATA_BYTE_A
    Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
  • RESTART_A
    This bit controls whether a RESTART is issued before the byte is sent or received.
  • STOP_A
    This bit controls whether a STOP is issued after the byte is sent or received.

Type Aliases§

  • CMD_R
    Field CMD reader - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
  • CMD_W
    Field CMD writer - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
  • DAT_R
    Field DAT reader - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
  • DAT_W
    Field DAT writer - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
  • FIRST_DATA_BYTE_R
    Field FIRST_DATA_BYTE reader - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
  • R
    Register IC_DATA_CMD reader
  • RESTART_R
    Field RESTART reader - This bit controls whether a RESTART is issued before the byte is sent or received.
  • RESTART_W
    Field RESTART writer - This bit controls whether a RESTART is issued before the byte is sent or received.
  • STOP_R
    Field STOP reader - This bit controls whether a STOP is issued after the byte is sent or received.
  • STOP_W
    Field STOP writer - This bit controls whether a STOP is issued after the byte is sent or received.
  • W
    Register IC_DATA_CMD writer