Module rp2040_pac::i2c0::ic_tx_abrt_source

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Expand description

I2C Transmit Abort Source Register

This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).

Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.

Structs§

Enums§

  • ABRT_7B_ADDR_NOACK_A
    This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
  • ABRT_10ADDR1_NOACK_A
    This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
  • ABRT_10ADDR2_NOACK_A
    This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.
  • ABRT_10B_RD_NORSTRT_A
    This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
  • ABRT_GCALL_NOACK_A
    This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.
  • ABRT_GCALL_READ_A
    This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
  • ABRT_HS_ACKDET_A
    This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
  • ABRT_HS_NORSTRT_A
    This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
  • ABRT_MASTER_DIS_A
    This field indicates that the User tries to initiate a Master operation with the Master mode disabled.
  • ABRT_SBYTE_ACKDET_A
    This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
  • ABRT_SBYTE_NORSTRT_A
    To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.
  • ABRT_SLVFLUSH_TXFIFO_A
    This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
  • ABRT_SLVRD_INTX_A
    1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
  • ABRT_SLV_ARBLOST_A
    This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never ‘owns’ the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.
  • ABRT_TXDATA_NOACK_A
    This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
  • ABRT_USER_ABRT_A
    This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])
  • ARB_LOST_A
    This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.

Type Aliases§

  • ABRT_7B_ADDR_NOACK_R
    Field ABRT_7B_ADDR_NOACK reader - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
  • ABRT_10ADDR1_NOACK_R
    Field ABRT_10ADDR1_NOACK reader - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
  • ABRT_10ADDR2_NOACK_R
    Field ABRT_10ADDR2_NOACK reader - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.
  • ABRT_10B_RD_NORSTRT_R
    Field ABRT_10B_RD_NORSTRT reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
  • ABRT_GCALL_NOACK_R
    Field ABRT_GCALL_NOACK reader - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.
  • ABRT_GCALL_READ_R
    Field ABRT_GCALL_READ reader - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
  • ABRT_HS_ACKDET_R
    Field ABRT_HS_ACKDET reader - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
  • ABRT_HS_NORSTRT_R
    Field ABRT_HS_NORSTRT reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
  • ABRT_MASTER_DIS_R
    Field ABRT_MASTER_DIS reader - This field indicates that the User tries to initiate a Master operation with the Master mode disabled.
  • ABRT_SBYTE_ACKDET_R
    Field ABRT_SBYTE_ACKDET reader - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
  • ABRT_SBYTE_NORSTRT_R
    Field ABRT_SBYTE_NORSTRT reader - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.
  • ABRT_SLVFLUSH_TXFIFO_R
    Field ABRT_SLVFLUSH_TXFIFO reader - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
  • ABRT_SLVRD_INTX_R
    Field ABRT_SLVRD_INTX reader - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
  • ABRT_SLV_ARBLOST_R
    Field ABRT_SLV_ARBLOST reader - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never ‘owns’ the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.
  • ABRT_TXDATA_NOACK_R
    Field ABRT_TXDATA_NOACK reader - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
  • ABRT_USER_ABRT_R
    Field ABRT_USER_ABRT reader - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])
  • ARB_LOST_R
    Field ARB_LOST reader - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.
  • R
    Register IC_TX_ABRT_SOURCE reader
  • TX_FLUSH_CNT_R
    Field TX_FLUSH_CNT reader - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.