Type Alias rp2040_pac::pll_sys::cs::W

pub type W = W<CS_SPEC>;

Register CS writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn refdiv(&mut self) -> REFDIV_W<'_, CS_SPEC>

Bits 0:5 - Divides the PLL input reference clock.
Behaviour is undefined for div=0.
PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

pub fn bypass(&mut self) -> BYPASS_W<'_, CS_SPEC>

Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual