Struct rp2040_pac::pll_sys::cs::CS_SPEC

pub struct CS_SPEC;

Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz

You can read this register and get cs::R. You can reset, write, write_with_zero this register using cs::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for CS_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CS_SPEC

reset() method sets CS to value 0x01

const RESET_VALUE: u32 = 1u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for CS_SPEC

write(|w| ..) method takes cs::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for CS_SPEC

read() method returns cs::R reader structure