Expand description
Miscellaneous Control Register
Modules§
- LSB of Post-divider for Audio PLL
- MSB of Post-divider for Audio PLL
- Default value of “0”
- This field defines the brown out voltage offset for the CORE power domain
- Reg0 brownout status bit.
- Enables the brownout detection.
- Number of clock periods (24MHz clock).
- This field defines the brown out voltage offset for the xPU power domain
- Reg1 brownout status bit.
- Enables the brownout detection.
- Number of clock periods (24MHz clock).
- This field defines the brown out voltage offset for the xPU power domain
- Reg2 brownout status bit.
- Enables the brownout detection.
- Signals that the voltage is above the brownout level for the SOC supply
- Number of clock periods (24MHz clock).