Module REG_CORE

Digital Regulator Core Register

Modules

FET_ODRIVE

If set, increases the gate drive on power gating FETs to reduce leakage in the off state

RAMP_RATE

Regulator voltage ramp rate.

REG0_ADJ

This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

REG0_TARG

This field defines the target voltage for the ARM core power domain

REG1_ADJ

This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

REG1_TARG

This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

REG2_ADJ

This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

REG2_TARG

This field defines the target voltage for the SOC power domain