Type Alias INPUT_SYNC_BYPASS

pub type INPUT_SYNC_BYPASS = Reg<INPUT_SYNC_BYPASS_SPEC>;

INPUT_SYNC_BYPASS (rw) register accessor: There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all zeroes.

You can read this register and get input_sync_bypass::R. You can reset, write, write_with_zero this register using input_sync_bypass::W. You can also modify this register. See API.

For information about available fields see input_sync_bypass module

Aliased Type

struct INPUT_SYNC_BYPASS { /* private fields */ }

Implementations

impl<REG: Resettable + Writable> Reg<REG>

pub fn reset(&self)

Writes the reset value to Writable register.

Resets the register to its initial state.

pub fn write<F>(&self, f: F)

where F: FnOnce(&mut W<REG>) -> &mut W<REG>,

Writes bits to a Writable register.

You can write raw bits into a register:

periph.reg.write(|w| unsafe { w.bits(rawbits) });

or write only the fields you need:

periph.reg.write(|w| w
    .field1().bits(newfield1bits)
    .field2().set_bit()
    .field3().variant(VARIANT)
);

or an alternative way of saying the same:

periph.reg.write(|w| {
    w.field1().bits(newfield1bits);
    w.field2().set_bit();
    w.field3().variant(VARIANT)
});

In the latter case, other fields will be set to their reset value.

impl<REG: Writable> Reg<REG>

pub unsafe fn write_with_zero<F>(&self, f: F)

where F: FnOnce(&mut W<REG>) -> &mut W<REG>,

Writes 0 to a Writable register.

Similar to write, but unused bits will contain 0.

Safety

Unsafe to use with registers which don’t allow to write 0.

impl<REG: Readable + Writable> Reg<REG>

pub fn modify<F>(&self, f: F)

where for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,

Modifies the contents of the register by reading and then writing it.

E.g. to do a read-modify-write sequence to change parts of a register:

periph.reg.modify(|r, w| unsafe { w.bits(
   r.bits() | 3
) });

or

periph.reg.modify(|_, w| w
    .field1().bits(newfield1bits)
    .field2().set_bit()
    .field3().variant(VARIANT)
);

or an alternative way of saying the same:

periph.reg.modify(|_, w| {
    w.field1().bits(newfield1bits);
    w.field2().set_bit();
    w.field3().variant(VARIANT)
});

Other fields will have the value they had before the call to modify.

impl<REG: RegisterSpec> Reg<REG>

pub fn as_ptr(&self) -> *mut REG::Ux

Returns the underlying memory address of register.

let reg_ptr = periph.reg.as_ptr();

impl<REG: Readable> Reg<REG>

pub fn read(&self) -> R<REG>

Reads the contents of a Readable register.

You can read the raw contents of a register by using bits:

let bits = periph.reg.read().bits();

or get the content of a particular field of a register:

let reader = periph.reg.read();
let bits = reader.field1().bits();
let flag = reader.field2().bit_is_set();

Trait Implementations

impl Debug for Reg<INPUT_SYNC_BYPASS_SPEC>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<REG: RegisterSpec> Send for Reg<REG>

where REG::Ux: Send,