Module rp2040_pac::pio0::input_sync_bypass

There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all zeroes.

Structs

• INPUT_SYNC_BYPASS_SPEC
  There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
  0 -> input is synchronized (default)
  1 -> synchronizer is bypassed
  If in doubt, leave this register as all zeroes.

Type Aliases

• R
  Register INPUT_SYNC_BYPASS reader
• W
  Register INPUT_SYNC_BYPASS writer