Struct rp2040_pac::pio0::RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Expand description

Register block

Implementations§

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impl RegisterBlock

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pub const fn ctrl(&self) -> &CTRL

0x00 - PIO control register

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pub const fn fstat(&self) -> &FSTAT

0x04 - FIFO status register

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pub const fn fdebug(&self) -> &FDEBUG

0x08 - FIFO debug register

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pub const fn flevel(&self) -> &FLEVEL

0x0c - FIFO levels

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pub const fn txf(&self, n: usize) -> &TXF

0x10..0x20 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

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pub fn txf_iter(&self) -> impl Iterator<Item = &TXF>

Iterator for array of: 0x10..0x20 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.

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pub const fn rxf(&self, n: usize) -> &RXF

0x20..0x30 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

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pub fn rxf_iter(&self) -> impl Iterator<Item = &RXF>

Iterator for array of: 0x20..0x30 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.

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pub const fn irq(&self) -> &IRQ

0x30 - State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There’s no fixed association between flags and state machines – any state machine can use any flag.

Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts – see e.g. IRQ0_INTE.

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pub const fn irq_force(&self) -> &IRQ_FORCE

0x34 - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.

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pub const fn input_sync_bypass(&self) -> &INPUT_SYNC_BYPASS

0x38 - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all zeroes.

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pub const fn dbg_padout(&self) -> &DBG_PADOUT

0x3c - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

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pub const fn dbg_padoe(&self) -> &DBG_PADOE

0x40 - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.

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pub const fn dbg_cfginfo(&self) -> &DBG_CFGINFO

0x44 - The PIO hardware has some free parameters that may vary between chip products.
These should be provided in the chip datasheet, but are also exposed here.

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