Struct rp2040_pac::pio0::input_sync_bypass::INPUT_SYNC_BYPASS_SPEC

pub struct INPUT_SYNC_BYPASS_SPEC;

There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all zeroes.

You can read this register and get input_sync_bypass::R. You can reset, write, write_with_zero this register using input_sync_bypass::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for INPUT_SYNC_BYPASS_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for INPUT_SYNC_BYPASS_SPEC

reset() method sets INPUT_SYNC_BYPASS to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for INPUT_SYNC_BYPASS_SPEC

write(|w| ..) method takes input_sync_bypass::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for INPUT_SYNC_BYPASS_SPEC

read() method returns input_sync_bypass::R reader structure