and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30…35 (the QSPI IOs).
You can read
this register and get proc_in_sync_bypass_hi::R
. You can reset
, write
, write_with_zero
this register using proc_in_sync_bypass_hi::W
. You can also modify
this register. See API.
reset()
method sets PROC_IN_SYNC_BYPASS_HI to value 0
write(|w| ..)
method takes proc_in_sync_bypass_hi::W
writer structure
1
and are changed if you pass 0
0
and are changed if you pass 1
read()
method returns proc_in_sync_bypass_hi::R
reader structure