Type Alias rp2040_pac::sio::interp0_ctrl_lane0::W
source · pub type W = W<INTERP0_CTRL_LANE0_SPEC>;
Expand description
Register INTERP0_CTRL_LANE0
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn shift(&mut self) -> SHIFT_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn shift(&mut self) -> SHIFT_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bits 0:4 - Logical right-shift applied to accumulator before masking
sourcepub fn mask_lsb(&mut self) -> MASK_LSB_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn mask_lsb(&mut self) -> MASK_LSB_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)
sourcepub fn mask_msb(&mut self) -> MASK_MSB_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn mask_msb(&mut self) -> MASK_MSB_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)
Setting MSB < LSB may cause chip to turn inside-out
sourcepub fn signed(&mut self) -> SIGNED_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn signed(&mut self) -> SIGNED_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
sourcepub fn cross_input(&mut self) -> CROSS_INPUT_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn cross_input(&mut self) -> CROSS_INPUT_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bit 16 - If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.
Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
sourcepub fn cross_result(&mut self) -> CROSS_RESULT_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn cross_result(&mut self) -> CROSS_RESULT_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bit 17 - If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
sourcepub fn add_raw(&mut self) -> ADD_RAW_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn add_raw(&mut self) -> ADD_RAW_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
sourcepub fn force_msb(&mut self) -> FORCE_MSB_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn force_msb(&mut self) -> FORCE_MSB_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.
No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
of pointers into flash or SRAM.
sourcepub fn blend(&mut self) -> BLEND_W<'_, INTERP0_CTRL_LANE0_SPEC>
pub fn blend(&mut self) -> BLEND_W<'_, INTERP0_CTRL_LANE0_SPEC>
Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled:
- LANE1 result is a linear interpolation between BASE0 and BASE1, controlled
by the 8 LSBs of lane 1 shift and mask value (a fractional number between
0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
- FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)
LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.