Type Alias rp2040_pac::i2c0::ic_tx_abrt_source::R

pub type R = R<IC_TX_ABRT_SOURCE_SPEC>;

Register IC_TX_ABRT_SOURCE reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn abrt_7b_addr_noack(&self) -> ABRT_7B_ADDR_NOACK_R

Bit 0 - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

pub fn abrt_10addr1_noack(&self) -> ABRT_10ADDR1_NOACK_R

Bit 1 - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

pub fn abrt_10addr2_noack(&self) -> ABRT_10ADDR2_NOACK_R

Bit 2 - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

pub fn abrt_txdata_noack(&self) -> ABRT_TXDATA_NOACK_R

Bit 3 - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

pub fn abrt_gcall_noack(&self) -> ABRT_GCALL_NOACK_R

Bit 4 - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

pub fn abrt_gcall_read(&self) -> ABRT_GCALL_READ_R

Bit 5 - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

pub fn abrt_hs_ackdet(&self) -> ABRT_HS_ACKDET_R

Bit 6 - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).

Reset value: 0x0

Role of DW_apb_i2c: Master

pub fn abrt_sbyte_ackdet(&self) -> ABRT_SBYTE_ACKDET_R

Bit 7 - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).

Reset value: 0x0

Role of DW_apb_i2c: Master

pub fn abrt_hs_norstrt(&self) -> ABRT_HS_NORSTRT_R

Bit 8 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

pub fn abrt_sbyte_norstrt(&self) -> ABRT_SBYTE_NORSTRT_R

Bit 9 - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.

Reset value: 0x0

Role of DW_apb_i2c: Master

pub fn abrt_10b_rd_norstrt(&self) -> ABRT_10B_RD_NORSTRT_R

Bit 10 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.

Reset value: 0x0

Role of DW_apb_i2c: Master-Receiver

pub fn abrt_master_dis(&self) -> ABRT_MASTER_DIS_R

Bit 11 - This field indicates that the User tries to initiate a Master operation with the Master mode disabled.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Master-Receiver

pub fn arb_lost(&self) -> ARB_LOST_R

Bit 12 - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter

pub fn abrt_slvflush_txfifo(&self) -> ABRT_SLVFLUSH_TXFIFO_R

Bit 13 - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.

Reset value: 0x0

Role of DW_apb_i2c: Slave-Transmitter

pub fn abrt_slv_arblost(&self) -> ABRT_SLV_ARBLOST_R

Bit 14 - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never ‘owns’ the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.

Reset value: 0x0

Role of DW_apb_i2c: Slave-Transmitter

pub fn abrt_slvrd_intx(&self) -> ABRT_SLVRD_INTX_R

Bit 15 - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.

Reset value: 0x0

Role of DW_apb_i2c: Slave-Transmitter

pub fn abrt_user_abrt(&self) -> ABRT_USER_ABRT_R

Bit 16 - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

pub fn tx_flush_cnt(&self) -> TX_FLUSH_CNT_R

Bits 23:31 - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter