Struct rp2040_pac::adc::div::DIV_SPEC

pub struct DIV_SPEC;

Clock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256

You can read this register and get div::R. You can reset, write, write_with_zero this register using div::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for DIV_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for DIV_SPEC

reset() method sets DIV to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for DIV_SPEC

write(|w| ..) method takes div::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for DIV_SPEC

read() method returns div::R reader structure