Module imxrt_ral::usbphy::CTRL_CLR

USB PHY General Control Register

Modules

• CLKGATE
  Gate UTMI Clocks
• DATA_ON_LRADC
  Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.
• DEVPLUGIN_IRQ
  Indicates that the device is connected
• DEVPLUGIN_POLARITY
  For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
• ENAUTOCLR_CLKGATE
  Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
• ENAUTOCLR_PHY_PWD
  Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
• ENAUTO_PWRON_PLL
  Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended
• ENDEVPLUGINDETECT
  For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
• ENDPDMCHG_WKUP
  Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
• ENHOSTDISCONDETECT
  For host mode, enables high-speed disconnect detector
• ENIDCHG_WKUP
  Enables the feature to wakeup USB if ID is toggled when USB is suspended.
• ENIRQDEVPLUGIN
  Enables interrupt for the detection of connectivity to the USB line.
• ENIRQHOSTDISCON
  Enables interrupt for detection of disconnection to Device when in high-speed host mode
• ENIRQRESUMEDETECT
  Enables interrupt for detection of a non-J state on the USB line
• ENIRQWAKEUP
  Enables interrupt for the wakeup events.
• ENOTGIDDETECT
  Enables circuit to detect resistance of MiniAB ID pin.
• ENOTG_ID_CHG_IRQ
  Enable OTG_ID_CHG_IRQ.
• ENUTMILEVEL2
  Enables UTMI+ Level2. This should be enabled if needs to support LS device
• ENUTMILEVEL3
  Enables UTMI+ Level3
• ENVBUSCHG_WKUP
  Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
• FSDLL_RST_EN
  Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
• HOSTDISCONDETECT_IRQ
  Indicates that the device has disconnected in high-speed mode
• HOST_FORCE_LS_SE0
  Forces the next FS packet that is transmitted to have a EOP with LS timing
• OTG_ID_CHG_IRQ
  OTG ID change interrupt. Indicates the value of ID pin changed.
• OTG_ID_VALUE
  Almost same as OTGID_STATUS in USBPHYx_STATUS Register
• RESUMEIRQSTICKY
  Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
• RESUME_IRQ
  Indicates that the host is sending a wake-up after suspend
• RSVD1
  Reserved.
• SFTRST
  Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers
• UTMI_SUSPENDM
  Used by the PHY to indicate a powered-down state
• WAKEUP_IRQ
  Indicates that there is a wakeup event