Module imxrt_ral::usbphy::CTRL_TOG

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USB PHY General Control Register

Modules§

  • Gate UTMI Clocks
  • Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.
  • Indicates that the device is connected
  • For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
  • Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
  • Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
  • Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended
  • For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
  • Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
  • For host mode, enables high-speed disconnect detector
  • Enables the feature to wakeup USB if ID is toggled when USB is suspended.
  • Enables interrupt for the detection of connectivity to the USB line.
  • Enables interrupt for detection of disconnection to Device when in high-speed host mode
  • Enables interrupt for detection of a non-J state on the USB line
  • Enables interrupt for the wakeup events.
  • Enables circuit to detect resistance of MiniAB ID pin.
  • Enable OTG_ID_CHG_IRQ.
  • Enables UTMI+ Level2. This should be enabled if needs to support LS device
  • Enables UTMI+ Level3
  • Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
  • Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
  • Indicates that the device has disconnected in high-speed mode
  • Forces the next FS packet that is transmitted to have a EOP with LS timing
  • OTG ID change interrupt. Indicates the value of ID pin changed.
  • Almost same as OTGID_STATUS in USBPHYx_STATUS Register
  • Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
  • Indicates that the host is sending a wake-up after suspend
  • Reserved.
  • Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers
  • Used by the PHY to indicate a powered-down state
  • Indicates that there is a wakeup event