Expand description
USB PHY Debug Register
Modules§
- CLKGATE
- Gate Test Clocks
- DEBUG_
INTERFACE_ HOLD - Use holding registers to assist in timing for external UTMI interface.
- ENHSTPULLDOWN
- Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
- ENSQUELCHRESET
- Set bit to allow squelch to reset high-speed receive.
- ENTX2RXCOUNT
- Set this bit to allow a countdown to transition in between TX and RX.
- HOST_
RESUME_ DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
- HSTPULLDOWN
- Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
- OTGIDPIOLOCK
- Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
- RSVD0
- Reserved.
- RSVD1
- Reserved.
- RSVD2
- Reserved.
- RSVD3
- Reserved.
- SQUELCHRESETCOUNT
- Delay in between the detection of squelch to the reset of high-speed RX.
- SQUELCHRESETLENGTH
- Duration of RESET in terms of the number of 480-MHz cycles.
- TX2RXCOUNT
- Delay in between the end of transmit to the beginning of receive