Expand description
Module Control Register 0
Modules§
- AHBGRANTWAIT
- Timeout wait cycle for AHB command grant.
- ARDFEN
- Enable AHB bus Read Access to IP RX FIFO.
- ATDFEN
- Enable AHB bus Write Access to IP TX FIFO.
- COMBINATIONEN
- This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
- DOZEEN
- Doze mode enable bit
- HSEN
- Half Speed Serial Flash access Enable.
- IPGRANTWAIT
- Time out wait cycle for IP command grant.
- MDIS
- Module Disable
- RXCLKSRC
- Sample Clock source selection for Flash Reading
- SCKFREERUNEN
- This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
- SERCLKDIV
- The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
- SWRESET
- Software Reset