rp2040_pac::xip_ctrl::stream_fifo

Struct STREAM_FIFO_SPEC

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pub struct STREAM_FIFO_SPEC;
Expand description

FIFO stream data
Streamed data is buffered here, for retrieval by the system DMA.
This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
the DMA to bus stalls caused by other XIP traffic.

You can read this register and get stream_fifo::R. See API.

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impl RegisterSpec for STREAM_FIFO_SPEC

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type Ux = u32

Raw register type (u8, u16, u32, …).
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impl Resettable for STREAM_FIFO_SPEC

reset() method sets STREAM_FIFO to value 0

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const RESET_VALUE: u32 = 0u32

Reset value of the register.
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fn reset_value() -> Self::Ux

Reset value of the register.
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impl Readable for STREAM_FIFO_SPEC

read() method returns stream_fifo::R reader structure

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