Struct rp2040_pac::xip_ctrl::ctr_hit::CTR_HIT_SPEC

pub struct CTR_HIT_SPEC;

Cache Hit counter
A 32 bit saturating counter that increments upon each cache hit,
i.e. when an XIP access is serviced directly from cached data.
Write any value to clear.

You can read this register and get ctr_hit::R. You can reset, write, write_with_zero this register using ctr_hit::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for CTR_HIT_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CTR_HIT_SPEC

reset() method sets CTR_HIT to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for CTR_HIT_SPEC

write(|w| ..) method takes ctr_hit::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for CTR_HIT_SPEC

read() method returns ctr_hit::R reader structure