Struct rp2040_pac::syscfg::proc_in_sync_bypass::PROC_IN_SYNC_BYPASS_SPEC

pub struct PROC_IN_SYNC_BYPASS_SPEC;

For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0…29.

You can read this register and get proc_in_sync_bypass::R. You can reset, write, write_with_zero this register using proc_in_sync_bypass::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for PROC_IN_SYNC_BYPASS_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for PROC_IN_SYNC_BYPASS_SPEC

reset() method sets PROC_IN_SYNC_BYPASS to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for PROC_IN_SYNC_BYPASS_SPEC

write(|w| ..) method takes proc_in_sync_bypass::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for PROC_IN_SYNC_BYPASS_SPEC

read() method returns proc_in_sync_bypass::R reader structure