Struct rp2040_pac::sio::interp0_base_1and0::INTERP0_BASE_1AND0_SPEC

pub struct INTERP0_BASE_1AND0_SPEC;

On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.

You can reset, write, write_with_zero this register using interp0_base_1and0::W. See API.

Trait Implementations

impl RegisterSpec for INTERP0_BASE_1AND0_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for INTERP0_BASE_1AND0_SPEC

reset() method sets INTERP0_BASE_1AND0 to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for INTERP0_BASE_1AND0_SPEC

write(|w| ..) method takes interp0_base_1and0::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1