Struct rp2040_pac::pio0::sm::sm_clkdiv::SM_CLKDIV_SPEC

pub struct SM_CLKDIV_SPEC;

Clock divisor register for state machine 0
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

You can read this register and get sm_clkdiv::R. You can reset, write, write_with_zero this register using sm_clkdiv::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for SM_CLKDIV_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for SM_CLKDIV_SPEC

reset() method sets SM_CLKDIV to value 0x0001_0000

const RESET_VALUE: u32 = 65_536u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for SM_CLKDIV_SPEC

write(|w| ..) method takes sm_clkdiv::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for SM_CLKDIV_SPEC

read() method returns sm_clkdiv::R reader structure