Module sm_clkdiv

Source
Expand description

Clock divisor register for state machine 0
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

Structs§

SM_CLKDIV_SPEC
Clock divisor register for state machine 0
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

Type Aliases§

FRAC_R
Field FRAC reader - Fractional part of clock divisor
FRAC_W
Field FRAC writer - Fractional part of clock divisor
INT_R
Field INT reader - Effective frequency is sysclk/(int + frac/256).
Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
INT_W
Field INT writer - Effective frequency is sysclk/(int + frac/256).
Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
R
Register SM_CLKDIV reader
W
Register SM_CLKDIV writer