Struct rp2040_pac::clocks::clk_sys_selected::CLK_SYS_SELECTED_SPEC

pub struct CLK_SYS_SELECTED_SPEC;

Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

You can read this register and get clk_sys_selected::R. See API.

Trait Implementations

impl RegisterSpec for CLK_SYS_SELECTED_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CLK_SYS_SELECTED_SPEC

reset() method sets CLK_SYS_SELECTED to value 0x01

const RESET_VALUE: u32 = 1u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Readable for CLK_SYS_SELECTED_SPEC

read() method returns clk_sys_selected::R reader structure