Module HPCOMR

SNVS_HP Command Register

Modules

HAC_CLEAR

High Assurance Counter Clear When set, it clears the High Assurance Counter Register

HAC_EN

High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state

HAC_LOAD

High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register

HAC_STOP

High Assurance Counter Stop This bit can be set only when SSM is in soft fail state

LP_SWR

LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set

LP_SWR_DIS

LP Software Reset Disable When set, disables the LP software reset

MKS_EN

Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default

NPSWA_EN

Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only

PROG_ZMK

Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism

SSM_SFNS_DIS

SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state

SSM_ST

SSM State Transition Transition state of the system security monitor

SSM_ST_DIS

SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state

SW_FSV

Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation

SW_LPSV

LP Software Security Violation When set, SNVS_LP treats this bit as a security violation

SW_SV

Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation