Modules§
- Capture Compare A Register
- Capture Compare B Register
- Capture Compare X Register
- Capture Control A Register
- Capture Control B Register
- Capture Control X Register
- Counter Register
- Control Register
- Control 2 Register
- Capture Value 0 Register
- Capture Value 0 Cycle Register
- Capture Value 1 Register
- Capture Value 2 Register
- Capture Value 3 Register
- Capture Value 4 Register
- Capture Value 5 Register
- Capture Value 1 Cycle Register
- Capture Value 2 Cycle Register
- Capture Value 3 Cycle Register
- Capture Value 4 Cycle Register
- Capture Value 5 Cycle Register
- Fault Disable Mapping Register 0
- Fault Disable Mapping Register 1
- DMA Enable Register
- Deadtime Count Register 0
- Deadtime Count Register 1
- Fractional Value Register 1
- Fractional Value Register 2
- Fractional Value Register 3
- Fractional Value Register 4
- Fractional Value Register 5
- Fractional Control Register
- Initial Count Register
- Interrupt Enable Register
- Output Control Register
- Phase Delay Register
- Status Register
- Output Trigger Control Register
- Value Register 0
- Value Register 1
- Value Register 2
- Value Register 3
- Value Register 4
- Value Register 5
Structs§
- Cluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, SM?CTRL, SM?VAL0, SM?FRACVAL1, SM?VAL1, SM?FRACVAL2, SM?VAL2, SM?FRACVAL3, SM?VAL3, SM?FRACVAL4, SM?VAL4, SM?FRACVAL5, SM?VAL5, SM?FRCTRL, SM?OCTRL, SM?STS, SM?INTEN, SM?DMAEN, SM?TCTRL, SM?DISMAP0, SM?DISMAP1, SM?DTCNT0, SM?DTCNT1, SM?CAPTCTRLA, SM?CAPTCOMPA, SM?CAPTCTRLB, SM?CAPTCOMPB, SM?CAPTCTRLX, SM?CAPTCOMPX, SM?CVAL0, SM?CVAL0CYC, SM?CVAL1, SM?CVAL1CYC, SM?CVAL2, SM?CVAL2CYC, SM?CVAL3, SM?CVAL3CYC, SM?CVAL4, SM?CVAL4CYC, SM?CVAL5, SM?CVAL5CYC, SM?PHASEDLY